This application is related to Korean Application No. 1999-51875, filed Nov. 22, 1999, the disclosure of which is hereby incorporated herein by reference.
The present invention relates generally to integrated circuit, and more particularly to synchronization of integrated circuits that operate in response to a clock signal.
Synchronous dynamic random access memories (DRAMs) are widely used in the area of integrated circuits. A synchronous DRAM inputs data into a memory cell or outputs data from a memory cell during a valid data window in synchronization with a clock signal. As the clock frequency increases, the time difference or phase difference between the clock signal and the data signal (hereafter xe2x80x9cskewxe2x80x9d) may not decrease, but the valid data window may.
Skew may be caused by the delay within the synchronous DRAM, the signal transmission time of the printed circuit board (PCB) that the synchronous DRAM is mounted on, or the relative time difference between clock signals used in a memory controller and a synchronous DRAM. Skew may become relatively larger with respect to a decreasing valid data region.
The clock signal may be input through a single pin and then distributed throughout the entire device. Therefore, a clock signal at a portion of the device relatively far away from the input pin may have a large delay compared to a clock signal closer to the input pin. This delay makes it difficult to maintain synchronization among various parts of the synchronous DRAM.
One approach for maintaining synchronization is to implement the connection structure of a clock signal in the same manner as in the connection structure of a data line on a PCB, therefore the clock signal has as much skew as the data line. This approach is based on the idea that a clock signal is transmitted in the same direction as the data transmission, and thus two clock signals, i.e., a transmission clock signal Tclk and a reception clock signal Rclk will be provided. However, this method is disadvantageous because it may be difficult to control the timing between a master clock signal and a transmission clock signal Tclk or a reception clock signal Rclk, and additional circuits may be required to solve this problem, thereby increasing the cost of a device.
Another approach for maintaining synchronization is to implement the bidirectional data strobe method disclosed in an article by Kim et al, entitled A 64-Mbit, 640-Mbyte/s Bidirectional Data Strobed, Double-Data-Rate SDRAM With a 40-mW DLL for a 256-Mbyte Memory System, IEEE Journal of Solid State Circuits, Vol. 33, No. 11, November 1998, pp. 1703-1710. According to the bidirectional data strobe method, an additional signal referred to as a data strobe signal may be included in each device and transmitted in the same direction as the data transmission. However, this approach is also disadvantageous because it may be difficult to maintain a synchronous relation between a master clock signal and a data strobe signal. Accordingly, there is a need for an improved approach for synchronizing a data signal with a clock signal.
Integrated circuit memory devices according to embodiments of the invention include a data synchronization circuit comprising a modulator, a pulse width filter and a demodulator. The circuit is configured to generate a filter input signal as a first pulse train having pulses of nonequivalent widths, in response to a first clock signal and a data input signal that is out of phase relative to the first clock signal. The circuit is further configured to filter the filter input signal and generate a filter output signal as a second pulse train. Finally, the circuit generates a data output signal as a true or complementary time corrected version of the data input signal, in response to the filter output signal and a second clock signal. Accordingly, the data signal is synchronized with a clock signal without requiring the use of a transmission clock signal Tclk and a reception clock signal Rclk, or a data strobe signal.
Other embodiments of the data synchronization circuit include a modulator that generates a filter input signal as a first pulse train having pulses of nonequivalent widths, in response to a first clock signal and a data input signal that is out of phase relative to the first clock signal. A pulse width filter generates a filter output signal as a second pulse train, in response to the filter input signal. Finally, a demodulator generates a data output signal as a true or complementary time corrected version of the data input signal, in response to the filter output signal and a second clock signal.
In embodiments of the invention, the first clock signal and the second clock signal are in phase with each other and the data output signal is in phase with the first and second clock signals.
The pulse width filter includes a delay unit and a filter circuit. The delay unit generates a delayed filter input signal from the filter input signal. The delay unit comprises an inverter chain.
The filter circuit generates the filter output signal from the filter input signal and the delayed filter input signal. The filter circuit comprises a first filtering device that performs a boolean NAND operation on the filter input signal and the delayed filter input signal. A second filtering device performs a boolean OR operation on the filter input signal and the delayed filter input signal. A third filtering device performs a boolean NAND operation on the output of the first filtering device and the output of a fourth filtering device. Finally, the fourth filtering device performs a boolean NAND operation on the output of the second filtering device and the output of the third filtering device. The first filtering device may be a NAND gate, the second filtering device may be an OR gate, and the third and fourth filtering devices may be NAND gates.
The modulator and the demodulator perform a boolean XOR operations, which may be implemented using XOR gates.
According to other circuit embodiments of the present invention, the data synchronization circuit may further include a delay locked loop that generates the first clock signal that is a shifted version of the second clock signal, the first clock signal having a phase that leads the phase of the second clock signal.
The data output signal is in phase with the second clock signal and the pulse width filter comprises a delay unit. The delay provided by the delay unit of the pulse width filter is equivalent to the shift provided by the delay locked loop.
In other embodiments, the second clock signal comprises a delayed version of the first clock signal and edge of the first clock signal is in phase with the midpoint of the data output signal.
The data synchronization circuit further includes a first input buffer, a second input buffer and a delay control circuit. The first input buffer receives the data input signal and provides the data input signal to the modulator. The second input buffer receives the first clock signal and provides the first clock signal to the modulator, the variable delay unit, and the delay unit. The delay control circuit generates the second clock signal and the control voltage from the first clock signal.
The delay control circuit may include the variable delay unit, the delay unit, the phase detector and the charge pump. The variable delay unit generates the second clock signal in response to the control voltage.
The delay unit generates a delayed version of the first clock signal. The delay unit delays the first clock signal by xc2xc of the first clock cycle (Pi/2).
The phase detector generates the control signal in response to the second clock signal and the delayed version of the first clock signal. The phase detector may be realized as a D flip flop.
The charge pump generates the control voltage in response to the control signal. The charge pump may be realized as an integrator. The charge pump may comprise a capacitor that is responsive to the control signal such that the charge pump generates a large control voltage when the control signal is high and generates a small control voltage when the control signal is low.
The pulse width filter includes a delay that is responsive to the control voltage of the charge pump. The delay of the pulse width filter increases as the control voltage decreases and decreases as the control voltage increases.
According to other embodiments of the present invention, the data synchronization circuit may be included in a multi-bank memory device. The multi-bank memory device may include a data bus and a memory controller electrically coupled to the data bus. It may further include a first memory bank electrically coupled to the data bus at a first point thereon. The first memory bank may comprise a data synchronization circuit that is responsive to a global clock signal and a second memory bank electrically coupled to said data bus at a second point thereon.